Semiconductor industries have become increasingly lighter, smaller, and multi-functional, and have higher performance at low cost. One of key technologies required to come up with the tendency is an integrated circuit (IC) packaging technology.
IC packaging refers to packaging for protecting a semiconductor chip such as a single device or an integrated circuit formed by stacking various electronic circuits and wirings from various external environment such as dust, moisture, and electrical and mechanical load, forming signal input/output terminals to and from a main board using a lead frame or a printed circuit board (PCB), and molding the resultant structure using an encapsulant in order to optimize and maximize electrical performance of a semiconductor chip.
A packaging process to form a semiconductor package refers to a series of processes of connecting an external connection terminal to a semiconductor chip and sealing the semiconductor chip to protect the semiconductor chip from an external impact.
Recently, as electronic industries have advanced, semiconductor packages have been moving towards a reduction in size, weight, and manufacturing cost. Also, as application fields of semiconductor packages extend to digital image devices, MP3 players, mobile phones, and large storages, various types of semiconductor packages have been introduced. A ball grid array (BGA) package and a wafer level chip scale package (WLCSP), among the semiconductor packages, are most generalized semiconductor packages.
In the WLCSP, a structure in which solder balls are directly attached to a semiconductor chip is called a fan-in structure, and a structure in which some of solder balls are attached to a substrate outside of a semiconductor chip is called a fan-out structure.
FIGS. 1A through 1E are cross-sectional views sequentially illustrating a process of manufacturing a wafer level package according to a related art.
First, lower surfaces of individual chips 10 separated in a wafer state are attached to an upper surface of a carrier wafer (or a mold frame) 12 at predetermined intervals by using a double-sided adhesive tape 11 (please refer to FIG. 1A).
Next, all of the individual chips 10 are molded with a molding compound resin 20 such that upper surfaces and side surfaces of the chips 10 are encapsulated by the molding compound resin 20 having a predetermined thickness (please refer to FIG. 1B).
Subsequently, the molding compound resin 20 including the individual chips 10 are removed from the attachment surface of the carrier wafer to expose lower surfaces of the individual chips outwardly. In this state, a grinding process is performed to make the upper surface of the molding compound resin 20 and the lower surfaces of the individual chips 10 even, and a cleaning process is performed on the lower surfaces of the chips 10 (please refer to FIG. 1C).
Thereafter, a process of forming a redistribution layer (RDL), i.e., a metal line, and bumps 40 from a bonding pad of each chip 10 to a desired position of the lower surface of the molding compound resin 20 is performed (please refer to FIG. 1D).
The redistribution layer refers to a metal line extending outwardly from the bonding pad such that input/output terminals such as solder balls may be attached at wide pitches to thus solve a problem of an electrical short caused as the input/output terminals attached to bonding pads of the chips at fine pitches are in contact with each other.
Here, in general, a passivation layer is formed on a surface of each chip excluding the bonding pad, the redistribution layer is formed thereon through a plating process, and an insulating passivation layer preventing penetration of moisture or various foreign materials into the redistribution layer and a short circuit phenomenon between the redistribution layers is also formed thereon. A specific formation process thereof will be omitted.
Finally, a process of sawing is performed along sawing lines (boundary lines of the package of the molding compound resin), completing individual wafer level fan-out packages each including the individual chip 10, the molding compound resin 20 formed around the individual chip 10, the lower redistribution layer 30, and the bumps 40 (please refer to FIG. 1E).
However, in the related art wafer level package manufacturing process, since the process of molding the molding compound resin should be performed, the number of processes increases and an operation time is lengthened.
Also, since the molding compound resin serves as a wafer, the fan-out package is frequently warped during a bumping process, and in a worst case scenario, cracks are generated.